Technology-aware Design of Sram Memory Circuits

Today’s data-dominated multimedia and low-power applications require more memory than ever. On-chip SRAM memories begin to dominate the chip area and have become the focus of technology scaling. However, the physical limitations of the technology scaling jeopardise the further progress of microelectronics as scaling results in devices that start to leak and that become less predictable. Closely matched devices and small transistor sizes, which matter the most when designing SRAM memories, are the first to suffer from the side-effects of scaling. In addition, increasing leakage currents must be controlled to limit the static power consumption of the memories. The main goal of this work is to take these side-effects into account by understanding and modelling the impact of transistor variations and subthreshold leakage currents on the functionality and performance parameters of SRAM circuits. The use of technology information during the design of circuits is called technology-aware design. A classic answer of circuit designers to deal with variability is the well-known, worst-case design method. This method uses large design margins to guarantee that the design constraints on all performance parameters are met and this for all process corners. However, this method is based on overly pessimistic assumptions, which result in higher power consumption and more area-overhead. The increasing impact of leakage currents and transistor variations on the functionality and performance of SRAM circuits makes it for the worst-case design approach almost impossible to satisfy all conflicting constraints typical for SRAM design. Statistical circuit design is an alternative that allows to better incorporate the variability problem. This method makes it feasible to estimate the distributions of the performance parameters, based on transistor variations. In this way, it is possible to use more realistic design margins, which can result in gains for chip area and power consumption. In this work, we analyse statistical circuit optimisation for SRAM circuits. To obtain this goal, we characterise the behaviour of a short channel device to create a first-order analytical model of the transistor. We use this model to express performance parameters of small SRAM circuits in function of the transistor parameters. Next, we propagate the transistor parameter distributions to the perfor-